Static random access memories (“SRAMs”) or semiconductor memories include a plurality of cells disposed in rows and columns to form an array. SRAM cells include a plurality of transistors coupled to bit lines and word lines that are used to read and write a bit of data to the memory cell. Single-port SRAMs enable a single bit of data to be written to or read from a bit cell at a particular time. In contrast, a multi-port SRAM enables multiple reads or writes to occur at approximately the same time. Conventional multi-port SRAM structures include word lines (“WLs”) in different metal lines, which causes different capacitive loading due to the different metal length being used to route signals of the SRAM. Multi-port SRAM structures are larger and wider in the WL direction than a single-port SRAM structure. Due to the larger and wider WL direction for the multi-port SRAM, the aspect ratio of an SRAM array can be impacted during heavy WL loading, especially for wide input/output (“I/O”) designs. When compared with a single-port SRAM, the periphery logic circuitry of the multi-port SRAM is doubled. As such, multi-port SRAMs can occupy a larger area, and signal routing complexities can occur.